1. Field of the Invention
The present invention relates to a spread spectrum receiver for a software radio, more particularly to circuits for the analog despreading and direct conversion of a direct sequence radio-frequency (RF) spread spectrum signal based on a FET wide-band direct-conversion circuit and to circuits for PN (pseudo random noise) code synchronization and despreading for different types of direct sequence spread spectra.
2. Description of the Related Art
The basic concept of a software radio is to utilize as much digital processing as possible so that the radio can be easily re-configured to receive signals of different formats, i.e., different modulation, under software control. The radio is simplified greatly if a single stage of RF down-conversion is utilized. Recently novel circuits for direct conversion based on the utilization of FET based square-law detectors have been proposed (refer to document [1], and [2],:
[1] International Application No. PCT/JP00/03521 M. Abe, N. Sasho, D. Krupezevic, and V. Brankovic, [2] WO99/33166 ('99. Jul. 1). These circuits enable the realization of direct conversion circuits with much higher bandwidth and linearity than previously possible.
The use of a direct conversion circuit in the context of a direct sequence spread spectrum receiver has advantages far greater than the above advantages of a single stage converter. In addition to the single stage converter, the direct conversion circuit effectively acts as an analog correlator. This will result in a large reduction in the required processing speed for a spread spectrum receiver and the associated reduction in power consumption.
FIG. 1 is a block diagram of a conventional digital direct sequence spread spectrum receiver.
The direct sequence spread spectrum receiver 10 of FIG. 1 comprises a receiver antenna 11, an RF filter 12, a multi-stage down converter 13, an RF front-end noise reduction filter 14, a sample and analog to digital (A/D) converter 15, a PN code synchronization and tracking circuit 16, and a Rake receiver (demodulator) 17.
As shown in FIG. 1, the typical implementation of a direct sequence spread spectrum receiver 10 includes the RF front-end noise reduction filter 14, followed by the sampler and A/D converter 15 operating at a frequency of some multiple of the chip rate, e.g., 8 times the chip rate. For wide-band CDMA (Code Division Multiple Access) at a 3× bandwidth, this chip rate is equal to 8×3.84=30.72 MHz. For a higher bandwidth, the rate can easily be greater than 100 MHz. The receiver runs the PN code synchronization and tracking circuits 16 and performs despreading digitally at these rates.
If the receiver utilizes antenna diversity, or a digital beam-forming array, then this circuitry is repeated at each of the array elements. For a large spreading bandwidth, the circuit complexity and the associated power consumption becomes large.
It becomes advantageous to design a receiver that operates at clock frequencies that are multiples of the symbol rate rather than the chip rate. This is possible if the despreading is effectively implemented in an analog form.